System, methods and apparatuses for in situ electrochemical imaging

ABSTRACT

Systems, methods and apparatuses described herein generally provide a millimetre size package-free complementary metal-oxide-semiconductor (“CMOS”) chip (referred to as a “die”) for the in situ (on-site) measurement or imaging of electrochemically detectable analytes.

TECHNICAL FIELD

Systems, methods and apparatuses for in situ measurement and imaging of electrochemically detectable analytes.

BACKGROUND

Micro-scale chips can be implanted or otherwise positioned in situ on a subject to measure target analytes. Integrating measurement functions of laboratory techniques into micro-scale implantable chips has myriad possible advantages, including added convenience and accuracy of measurement. Excessive power draw from components of implantable micro-scale chips can limit utility.

SUMMARY

In one aspect, an integrated circuit for electrochemically measuring target analytes in a subject is provided, the integrated circuit comprising: a recording module array coupled to a plurality of microelectrodes disposable on, in or adjacent to the subject for recording analog signals relating to chemically bonded analytes of the subject; an op-amp-less delta-sigma-ADC-based potentiostat circuit for providing a digitized representation of the recorded analog signals, the potentiostat circuit comprising: an op-amp less integrator circuit coupled to the recording module array, the integrator circuit comprising a grounded capacitor for integration of the recorded analog signal; a comparator coupled to an output of the integrator circuit to reduce signal distortion thereof; a digital-to-analog converter providing a negative feedback loop from an output of the comparator to the output of the integrator circuit; and a pulse shaping block providing an output signal of the potentiostat; and an impedance spectroscopy circuit coupled to the output signal of potentiostat comprising a 1 bit XOR gate and a counter for receiving a waveform and the output signal, and providing a 1 bit multiplication of the output signal.

In another aspect, a potentiostat circuit is provided, the potentiostat circuit comprising: an op-amp-less integrator circuit comprising a grounded capacitor for integration of the recorded analog signal; a comparator coupled to an output of the integrator circuit to reduce signal distortion thereof; a digital-to-analog converter providing a negative feedback loop from an output of the comparator to the output of the integrator circuit; and a pulse shaping block providing an output signal of the potentiostat.

In a further aspect, an integrated circuit for electrochemically measuring target analytes of a subject is provided, the integrated circuit comprising: a power coil for receiving power from a receiver device by magnetic induction; a microelectrode array and an associated amperometric channel array for measuring the target analytes of the subject and generating sensor readings; and a transmitter for wirelessly transmitting sensor readings to the receiver device.

In yet another aspect, a method for in situ electrochemical imaging of target analytes of a subject is provided, the method comprising: implanting an integrated circuit on, in or adjacent to a targeted region of the subject, the integrated circuit comprising: a power coil for receiving power from a receiver device by magnetic induction; a microelectrode array and an associated amperometric channel array for measuring the target analytes of the subject and generating sensor readings; and a transmitter for transmitting sensor readings to the receiver device; positioning the receiver device on a surface of the subject; receiving sensor readings at the receiver device; and processing the sensor readings to diagnose risk of seizure onset in the subject.

These and other aspects are contemplated and described herein. It will be appreciated that the foregoing summary sets out representative aspects of systems, methods, apparatuses for in situ electrochemical imaging to assist skilled readers in understanding the following detailed description.

DESCRIPTION OF THE DRAWINGS

A greater understanding of the embodiments will be had with reference to the Figures, in which:

FIG. 1 shows a block diagram of an embodiment of a system for in situ electrochemical imaging;

FIG. 2 shows an embodiment of a method for in situ electrochemical imaging;

FIG. 3 shows application of a system for in situ electrochemical imaging for selective imaging of the concentrations of potassium (K+) ions over sodium (Na+) ions;

FIG. 4 shows an embodiment of a two-stage system for in situ electrochemical imaging;

FIG. 5 shows an embodiment of a three-stage system for in situ electrochemical imaging;

FIG. 6 shows an embodiment of the intermediate receiver device for a system for in situ electrochemical imaging;

FIG. 7 shows an embodiment of a base station for a system for in situ electrochemical imaging comprising an inductive power transmission floor;

FIG. 8 shows a circuit for dynamic load tracking using reflected impedance monitoring for the embodiment of the base station;

FIG. 9 shows an implementation of a differential amplifier circuit for dynamic load tracking for the embodiment of the base station;

FIG. 10 shows a schematic level representation of a die for in situ electrochemical imaging;

FIG. 11 shows a layout level representation of a die for in situ electrochemical imaging;

FIG. 12 shows a fabricated die micrograph level representation of a die for in situ electrochemical imaging;

FIG. 13 shows an embodiment of an amperometric channel array of a die for in situ electrochemical imaging;

FIG. 14 shows circuit diagrams of an amperometric channel minimized in size and power consumption by merging circuit blocks;

FIG. 15 shows a block diagram of an amperometric channel implemented by a delta-sigma front-end ADC;

FIG. 16 shows a conventional implementation of a typical first order ADC used for amperometry;

FIG. 17 shows an op-amp-less delta-sigma ADC;

FIG. 18 shows a lumped model of an arbitrary passive medium under-test;

FIG. 19 shows a transient lumped RC model of the sample under test by an op-amp-less potentiostat;

FIG. 20 shows a discrete-time approximation of a source voltage signal in the model of FIGS. 18 to 19;

FIG. 21 shows the decomposition of a source signal of FIGS. 18 to 20 into constant voltage and step signal components;

FIG. 22 shows a z-domain model of an ideal integrator in a conventional ΔΣ-ADC-based potentiostat;

FIG. 23 shows a z-domain model of an integrator for an op-amp-less potentiostat;

FIG. 24 shows a z-domain model of a 1-bit DAC in the op-amp-less circuit;

FIG. 25 shows an ideal whole system model for a ΔΣ-ADC-based potentiostats;

FIG. 26 shows an op-amp less whole system model for a ΔΣ-ADC-based potentiostats;

FIG. 27 shows an implementation of a digital multiplication operation performed on the output of a delta sigma ADC after a decimation filter;

FIG. 28 shows the replacement of the 16-bit coefficient multiplication by a 1-bit XOR;

FIG. 29 illustrates decibels relative to full scale (“dbFS”) against frequency for a tone signal after down-conversion by an ideal sine wave signal;

FIG. 30 illustrates dbFS against frequency for a tone signal after down-conversion by a squarewave approximation of a sinewave signal;

FIG. 31 shows schematic diagrams of an amperometric channel implemented by conventional circuit blocks;

FIG. 32 shows schematic diagrams of an amperometric channel according to a power- and area-minimized implementation;

FIG. 33 shows a zero-kickback comparator circuit used to implement the delta-sigma ADC in the proposed channel;

FIG. 34 shows dynamic logic buffers and other pulse shaping circuits necessary for connecting the comparator output to other clock; and

FIG. 35 shows a block diagram of the charge pump to implement the I-DAC in the feedback.

DETAILED DESCRIPTION

For simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the Figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practised without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the embodiments described herein. Also, the description is not to be considered as limiting the scope of the embodiments described herein.

Various terms used throughout the present description may be read and understood as follows, unless the context indicates otherwise: “or” as used throughout is inclusive, as though written “and/or”; singular articles and pronouns as used throughout include their plural forms, and vice versa; similarly, gendered pronouns include their counterpart pronouns so that pronouns should not be understood as limiting anything described herein to use, implementation, performance, etc. by a single gender. Further definitions for terms may be set out herein; these may apply to prior and subsequent instances of those terms, as will be understood from a reading of the present description.

Any module, unit, component, server, computer, terminal or device exemplified herein that executes instructions may include or otherwise have access to computer readable media such as storage media, computer storage media, or data storage devices (removable and/or non-removable) such as, for example, magnetic disks, optical disks, or tape. Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. Examples of computer storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by an application, module, or both. Any such computer storage media may be part of the device or accessible or connectable thereto. Further, unless the context clearly indicates otherwise, any processor or controller set out herein may be implemented as a singular processor or as a plurality of processors. The plurality of processors may be arrayed or distributed, and any processing function referred to herein may be carried out by one or by a plurality of processors, even though a single processor may be exemplified. Any method, application or module herein described may be implemented using computer readable/executable instructions that may be stored or otherwise held by such computer readable media and executed by the one or more processors.

Embodiments described herein generally provide an integrated circuit for electrochemically measuring target analytes. More specifically, an embodiment is a millimetre size package-free complementary metal-oxide-semiconductor (“CMOS”) chip (referred to below as “die”) for the in situ (on-site) high-spatial resolution measurement or imaging of electrochemically detectable analytes, as well as associated systems, methods and apparatuses. These analytes may, for example, include cellular ions such as Na+, K+, Ca++ Mg; neurotransmitters such as dopamine and serotonin; glucose, insulin and other like molecules; electrolytes; drug concentrations; and other analytes such as glutamate, lactate, noradrenaline, acetylcholine, choline, etc. The term “in situ” includes disposing the integrated circuit or an electrode coupled to the integrated circuit on, in or adjacent to a target region of the subject such that analyte measurements can be obtained from the target region.

Embodiments of a die comprising an induction power coil, as well as an electrode array and an associated amperometric recording channel array for measuring target analytes are described. An inductive power transfer system and a short-range communication circuit power and communicate with the die simultaneously. Further, embodiments of an amperometric channel are described which may minimize size and power consumption by merging circuit blocks and simplifying the resulting schematic as compared to conventional designs based on known properties of the expected channel input signal. Circuit minimization steps are described, including providing a front-end digital op-amp-less potentiostat, and, with respect to the described channel's counter, approximating multiplication coefficients by a single bit approximation of those values.

Thus, embodiments described herein provide an ultra-low power op-amp-less delta-sigma-ADC-based potentiostat circuit. The delta-sigma-ADC-based potentiostat may consume approximately 50 Nanowatts of power. Compared with current op-amp-based potentiostats with the same noise performance, this op-amp-less circuit may provide a significant reduction of power consumption without comprising speed or noise performance as in some other ultra-low power designs. By removing the front-end op-amp, this design may maintain high-speed and low 1/f noise despite being ultra-low power. Moreover, as compared with some other non-amplifier-based ultra-low power potentiostats, this potentiostat may have faster response and lower power consumption. Some embodiments of the potentiostat may, in some circumstances, have more than 1000 times faster response and 50 times less power consumption than some other non-amplifier-based ultra-low power potentiostats.

Further, embodiments described herein provide a computationally-efficient impedance spectroscopy (“IS”) circuit which may minimize required computational power. Unlike conventional IS circuits which multiply the potentiostat output by high-resolution sin(ω_(o)t) and cos(ω_(o)t) waveforms, the described IS circuit only multiplies by a 1-bit waveform (“1” when sin(ω_(o)t)/cos(ω_(o)t)>1 and “0” when sin(ω_(o)t)/cos(ω_(o)t)<0). A single XOR gate replaces the many digital logic gates of conventional IS circuits.

Further, embodiments described herein provide a zero-hysteresis comparator circuit which may reduce or eliminate the signal distortion occurring due to removing the op-amp in embodiments of the potentiostat described herein. This circuit may reduce naturally occurring hysteresis in the comparator by isolating the output of the comparator from its input, which may minimize the impact of the previous comparator output on its current decision.

Referring now to FIG. 1, shown therein is a block diagram of an embodiment of a system 100 for in situ electrochemical imaging. The system 100 comprises a base station 102, an optional receiver device 104 and a die 106, the components and functionality of which will be described in more detail below. In use, the die may be positioned in situ for measurement of target analytes of a subject 112.

The die 106 comprises a recording module array 114 comprising chemically-sensitive microelectrodes 132 and associated potentiostat channels 134 for recording signals relating to chemically bonded analytes, a transmitter 115 for transmitting data relating to the sensor readings, a power coil 116 for receiving energy by magnetic induction from the receiver device 104 or base station 102, low-power electronics 121, and a bank of capacitors 119 for storing energy on the die to power the low-power electronics 121. More particularly, die 106 may be covered along a surface thereof with amperometric recording microelectrodes for bonding chemically with targeted analytes when the die is positioned at a location of interest of a subject 112, in situ, and activated.

The receiver device 104 comprises a transmitter 122, a receiver 124 and a power coil 118. The base station 102 comprises a receiver 126 and a power coil 120. The die 106, receiver device 104 and base station 102 comprise other components as set out in more detail below with reference to particular embodiments.

In the embodiment illustrated in FIG. 1, the die 106 transmits data comprising recorded signals (illustrated as block 108) to the receiver device 104, and receives power therefrom (illustrated as block 110). Similarly, the receiver device 104 transmits data received from the die to the base station 102 and receives power therefrom, as illustrated by blocks 109 and 111, respectively. The base station 102 may be communicatively linked over a wired or wireless network 130 with a computing device 128 for processing received data. Optionally, data may be processed locally at the base station 102 if the base station comprises hardware for processing the data. In embodiments described below, the die 106 may be directly linked with the base station 102.

Referring now to FIG. 2, shown therein is a method 220 for in situ electrochemical imaging. According to the method 220 at block 202 the die 106 is positioned at a location of interest in or on a subject 112. This location might, for example, be adjacent to the subject's eye, brain, or other tissue for which analyte monitoring is desired. At block 204 the die is activated by the placement of a receiver device 104 or base station 102 nearby and the transmission of power to the die. At block 206 the die records signals indicative of the concentration of target analytes, such as ions, molecules, or microorganisms within the particular location that make contact with the die microelectrodes. At block 208, the die sends out the recorded data using radio-frequency (“RF”) waves via the transmitter 115 to the receiver device 104 (or directly to the base station 102), positioned nearby, and preferably situated as close as possible to the die 106. At block 210, the data comprising the recorded signals may be buffered and re-transmitted to another RF receiver unit (referred to generally as base station 102) which could be farther away (e.g. meters or further) from the die 106 and the first receiver device 104. At block 212, the data may be stored in memory at the receiver device 104 (or base station 102, if re-transmitted at block 210). At block 214, the data may be processed, either at the receiver device 104, base station 102 or at a communicatively linked computing device, depending on the configuration of the system.

In the following discussion, reference will be made to various figures, each of which is to be referenced along with FIG. 1.

Referring now to FIG. 3, shown therein is a particular application of the system 100 for implementing method 220, applying the in situ CMOS die 106 for selective imaging of concentrations of potassium (K+) ions over sodium (Na+) ions across the implanted region on the cortex of a free-moving patient 112. The die surface takes a 2-dimensional image of analyte concentration profile by simultaneously conducting impedance spectroscopy at all individual microelectrode sites in parallel and converting the resulting signals to digital words at the electrode location in the die, which corresponds to actions carried out at block 206 of method 220. The digital bit stream created from all the microelectrodes data—i.e. impedance spectroscopy information from all individual on-chip microelectrodes in the die—is transmitted wirelessly outside the body to a receiver device 104, which corresponds to block 208. Specifically, a miniature radio comprising a transmitter on the die communicates the recorded information to the receiver device 104. As illustrated, the receiver device 104 may be worn and may be placed on the surface of the subject's skin 112 as close as practically possible to the implanted die. The receiver device 104 may thus be constructed as a flexible patch. The wearable receiver device 104 then re-transmits this information by a more powerful radio to a base station 102 such as a handheld unit or a PC for analysis and display and/or permanent storage, which corresponds to blocks 210, 212, 214. The ionic concentrations provided from the imaging information may be useful for the diagnosis and possible abortion of seizure onsets in patients with intractable epilepsy.

It will be understood that the application provided in FIG. 3 is merely illustrative. It is contemplated that the die 106 could also be used for in situ measurement in other locations of interest. For example, the die could be fabricated into a contact lens for measurement of glucose levels or other analytes along the surface of the eye. Description below of particular embodiments with respect to the application provided in FIG. 3 is not intended to be limiting.

Referring now to FIGS. 4 and 5, shown therein are further embodiments of systems for in situ electrochemical imaging 200, 250. The dimensions, power/current usage and bandwidth shown are exemplary and not intended as limiting. The embodiments shown illustrate a two stage system 200 and a three stage system 250 used to wirelessly link the die 106 to the base station 102. Depending on the application, the die 106 can communicate directly with the base station 102 in a two stage system illustrated in FIG. 4, comprising stages L1 and L2. Alternately, according to a three stage system comprising stages L1, L2 and L3, a receiver device 104 may be provided at a second intermediary stage L2, to link with the base station 102, as shown in FIG. 5.

The two stage system 200 may be used when the base station 102 can be located close to the die 106 (such as within a few centimeters). In applications where the base station 102 cannot be located close to the die at all times, the three stage system 250 can be used whereby a receiver device 104 is provided at an intermediate stage, as illustrated in FIG. 5 to relay the data from the die to the base station located some distance from the die (such as a few meters). An advantage of providing the receiver device 104 at an intermediate stage in a three stage system 250 is that it may improve the die performance and the wireless link quality in applications where the base station cannot be present near the die at all times. The intermediate stage is mobile, does not have an energy source attached to it, and is a fraction of the size of the base station. Therefore, in an application such as in FIG. 3, it can be permanently attached at the nearest point to the die to improve die performance and wireless link quality.

As described above with reference to FIG. 1, the energy to power the CMOS die 106 is delivered via magnetic induction from the receiver device 104 or base station 102 (illustrated as element 110 and 111, respectively). In the two stage system 200, the base station 102 generates an alternating magnetic field in coil 120 which is induced into an integrated power coil 116 in the die. The magnetic energy is then converted to electric energy which is stored on a bank of capacitors 119 on the die to power components of the die, including low-power electronics 121. In the three-stage system, the magnetic field created by the base station 102 is induced into a coil 118 in the intermediate stage device 104 which then refocuses the magnetic field to better power the CMOS die. Operable geometries for the magnetic coil in each stage, L1, L2, and L3, would be apparent to those of skill in the art and exemplary geometries are shown in FIG. 5 as 12 cm×12 cm for the base station 102 power coil 120 and 3 mm×3 mm for the die 106 power coil 116, and further geometries are described below.

Data transfer between the CMOS die 106 and the base station 102 or receiver device 104 at element 108 may take place using either of two low-power radio transmission techniques: (a) ultra-wideband pulse radio (“UWB-IR”) transmission, and (b) backscatter modulation techniques such as done in passive radio-frequency identification (“RFID”) tags. As indicated by element 108 in FIG. 4, the CMOS die 106 communicates the data directly to the base station 102 in the two stage system 200. A UWB-IR transmitter may be used in the two stage system to accomplish this. In the three stage system 250, the data may be backscattered to the intermediate stage at element 108 (as shown in FIG. 4). The data may then be relayed to the base station using a UWB-IR transmitter on the intermediate device 104 at element 109.

Referring now to FIGS. 6 to 9, embodiments and components of the receiver device 104 and base station 102 will be described before describing particular embodiments of the die 106 in subsequent figures.

Referring now to FIG. 6, shown therein is an embodiment of the intermediate receiver device 104. FIG. 6 shows particularly an embodiment of the receiver device 104 comprising a wireless interrogation microsystem developed on flexible printed circuit boards. As an example, the receiver device 104 may measure approximately 2 cm×2 cm×0.6 cm, as illustrated. During use the receiver device 104 may be worn directly on top of the implant die 106 at the closest point to the die on the exterior of the subject 112 as described above, such as on the surface of the skin. The receiver device 104 comprises an interrogation board 172 comprising a receiver 124 for receiving back telemetry data from the implanted K+ imaging die 106, a small low power short-range radio (optionally 10 mW) comprising a transmitter 122 which may be capable of transmitting up to 1 MBps to a nearby (such as up to 10 m) computer via wireless receiver (e.g., a USB port wireless transceiver dongle 126), and inductive power receiver coil 118 which may comprise a 16-layer spiral inductor developed on a flexible printed circuit board. The transmitted data may be received by the wireless receiver and can be plotted (e.g., in a MATLAB™ interface) for analysis. The coil 118 may include (be joined with) a wideband data coil operating at the third harmonic of the inductive power carrier. The coil 118 receives back telemetry data sent by the implant 106 while blocking the strong power carrier sent by the flexible inductive power receiver board on top of the miniPCB stack. The backtelemetry signal is processed and converted to digital data by the interrogation board.

Referring now to FIGS. 7 to 9, shown therein is a particular embodiment of the base station 102 providing an inductive power transmission floor 170 comprising an array of individual transmitting coils 120 and associated components developed on two-layer printed circuit board, configured and driven by a control board 174. The base station also comprises receivers 126 (e.g., a separate USB dongle). The inductive power transmission floor 170 provides power to the receiver device 104 and the die 106, such as an implanted die for K+ imaging. The floor 170 comprises an array of planar inductive transmitting coils 120 which may be located at the bottom of an environment housing a subject 112, an example of such an environment being the cage of an animal, to be tested with a die 106. The subject 112 can be dynamically tracked by an impedance sensing circuit in the control board 174 of the powering system. The impedance sensing circuit can continuously measure the impedance of each coil to determine whether a receiver device 104 is present. Once the power receiver is located, it may be powered by a coil closest to the receiver device 104. FIG. 8 illustrates a circuit for dynamic load tracking using reflected impedance monitoring as described above. Element 176 illustrates the circuit diagram when a receiver device 104 is not present in proximity to the transmission floor 170. Element 178 illustrates the circuit diagram when a receiver is present in proximity to the transmission floor 170, and the receiver's associated reflected load. FIG. 9 illustrates an implementation of a differential amplifier circuit for monitoring the supply voltage to measure the reflected impedance of the receiver.

Referring now to FIGS. 10 to 12, shown therein are illustrations of the die 106 at the schematic level (FIG. 10), layout-level (FIG. 11), and fabricated die micrograph level (FIG. 12). The configuration of the components of the die 106 and particularly the lower-power electronics 121 for providing the functionality described above will now be described in additional detail with respect to FIGS. 10 to 12.

As described above, the die 106 comprises a recording module array 114 comprising an array of electrodes 132, such as a 32×32 array, with a dedicated digital potentiostat channel 134 fabricated underneath each electrode (illustrated in FIG. 11, 13). The energy harvesting power coil 116 is fabricated around the electrode array. Low-power electronics 121 comprising components for peripheral clock generation and data processing, as well as power management circuits are fabricated around the potentiostat channel 134 array, underneath the energy harvesting coil 116. More particularly, the low-power electronics 121 in FIG. 10 are shown to comprise a delay-locked loop (“DLL”) 140, a timing sequence generator 142, a 13-bit counter 144, a divide-by-8 frequency divider 139, a decoder 146, an amplitude-modulated demodulator (“AM Demodulator”) 148, an analog to digital converter (“ADC”) 150, a low-pass filter (“LPF′”) 152, a rectifier 154, a backscatter modulator 156 and a multiplexer 158, the functionality of which will be described below. A storage capacitor bank 119 is also shown.

Referring now to FIG. 10 and describing in more detail the operation of a particular embodiment of the die 106, once the die is activated at block 204 of method 220, the potentiostat channels 134 of the recording module array 114 periodically record the electric charge accumulation on their corresponding microelectrode 132 and convert them to digital data, such as 16-bit digital words which can be stored in 16 D-flip-flops (not shown) fabricated inside each channel. After each conversion, the 16-bit content of all the channels may be extracted and serialized by a readout circuit (embodied in FIG. 10 by column decoder 136 and row multiplexer 158) The column decoder 136 illustrated above the array switches the content of the channels along each column onto the 16-bit bus lines 1002 running along the rows of the array. The multiplexer 158 sequentially reads out the row buses once they are switched onto the D-flip-flops inside the individual channels along the selected column. The multiplexer produces two serial outputs 1004 corresponding to the less significant and the more significant bytes of channels' 134 data words. The serial outputs of the multiplexer are fed into the on-chip radio transmitter 156 which sends the data out to the base station 102 (in the two-stage system), or the intermediate stage 104 (in the three-stage system).

With respect to the power management circuit of electronics 121, electric energy to power the die 106 microsystem in FIG. 10 may be generated by an integrated rectifier 154 which can convert AC voltage induced in the energy harvesting coil 116 into supply voltages, such as at 0.6V and 1.2V. Optionally, the 0.6V voltage may be used to power the all the digital circuits and the 1.2V supply can be used to power the analog signal processing and the RF front-end data communication circuits.

With respect to the clock generation of electronics 121, all the global clock, control and timing sequence signals may be generated from the alternating signal induced into the energy harvesting coil 116 using the clock generation blocks 148, 150. An illustrative 6.7 MHz signal of the coil 116 may be converted to a preferred global clock, such as an 875 kHz global clock by a frequency divider, such as a divide-by-8 frequency divider 139. The global clock may then then used by 13-bit counter 144 to generate all the 13-bit control signals for the MUX 158 and the decoder 136 in the readout circuit, as well as the 6 timing sequence signals used to run the individual digital potentiostat channels 134.

Referring now to FIG. 11, shown therein is an embodiment of the layout 550 of the CMOS die 106. On the top layer 552, the coil 116 is laid out around the periphery of the chip while the core of the chip is populated with the microelectrodes 132 comprising working electrodes 162 (“WE”) realized by 40 um×40 um aluminum pads on the top interconnect layer of the chip, as well as a long common reference microelectrode 164 (“RE”) which occupies the space in between the individual microelectrodes 132 and creates a two-electrode electrochemistry cell (i.e. working+reference electrodes) with each individual charge-sensing microelectrode. Underneath each individual microelectrode pad, as shown in middle layers (e.g., there may be, for example, 10 layers below top layer which are included in 554 and 556), there is a densely laid-out digital potentiostat channel 134 which transduces the charge on the aluminum pad above it. Element 554 provides an enlarged view of the middle layer 556.

Referring now to FIG. 12, shown therein is a micrograph of the fabricated CMOS die, according to a particular embodiment. The microelectrode array 132 and the energy harvesting coil 116 can be seen on the top level. There is an additional layer of auxiliary pads 166 directly above the microelectrode array which may be used for testing and fault finding purposes.

Referring now to FIG. 13, shown therein is an embodiment 600 of the amperometric channel array 134 for the die 106. The amperometric recording channels 134 are organized in the form of an array in the center of the die underneath the electrodes 132. The area is surrounded on the top layer by the power coil 116. The die may measure approximately 3 mm along dimensions 608, and 0.3 mm along its height 610. With regards to the electrodes 132, each column comprises 32 working electrodes 162 and one reference electrode 164 running along the side of the entire column. During amperometry, the reference electrode 164 is driven by a periodic voltage signal (sinusoid, ramp, or sawtooth) 604 while voltage of all the working electrodes 162 are held at a constant value (of approximately 300 mV to 500 mV). During operation, as shown in the diagram 602, the current flowing into the WE 162 as a result of its potential difference with the RE 164 is recorded by a front-end circuit 606 operating essentially as a transimpedance amplifier. The output of the transimpedance amplifier circuit 606 may be converted to digital words read by the array readout circuit after in-channel bandpass filtering.

Based on the embodiments of the die 106 described above, and the associated operational values for the components therein (particularly as described and illustrated in FIGS. 10 to 13), an approximately thousand channel implant die 106 may have approximately 0.08 uW power budget per channel 134 for use with amperometry (such as K+ amperometry), analog-to-digital-conversion and digital bandpass-filtering—which come up to approximately 100 uW in total power consumption for the die when including the power required for clock and bus generation and distribution circuits and data telemetry. Based on known values, a straightforward block-by-block implementation of the transimpedance amplifier, ADC, and digital bandpass filter will not meet the low-power, high-sensitivity, and small-size requirements of the in vivo K+ imaging system proposed here. The embodiments described below with reference to FIGS. 14 to 35 may meet some performance requirements by minimizing size and power consumption of each channel by merging circuit blocks and simplifying the resulting schematic based on the known properties of the expected channel input signal.

Referring to FIG. 14, shown therein are amperometric channel circuit diagrams. Embodiment 702 illustrates a conventional block diagram of an amperometric channel comprising a transimpedance amplifier 708 (“TIA”) (current “I” to voltage “V” converter), an ADC 710, a digital multiplication 712 and an accumulation circuit (counter) 714. Depending on the digital coefficient used, the output of the counter will represent the real or imaginary part of the input current with respect to the applied voltage signal at the reference. Embodiment 704 illustrates the block diagram of a simplified channel 134 where the size and power consumption have been reduced by performing a coefficient multiplication operation during the ADC operation in the mixed-signal domain.

The channel diagrammed at element 180 provides a further minimization of the amperometric channel using a delta-sigma front-end ADC, which may have significantly reduced size and power consumption. As compared with embodiment 704, in embodiment 180 the transimpedance stage has been incorporated into the ADC in block 182. By implementing the ADC in a delta-sigma topology, the front-end integrator is tasked with I-to-V conversion. The size and power requirements of the ADC itself may be further minimized by removing the front-end op-amp from a conventional implementation of the ADC and performing integration by a grounded capacitor, as described below. Further minimization of the size and power requirements of the circuit components may be achieved by approximating the multiplication coefficients by a single bit approximation of those values at block 184. As will be described below, in particular circumstances, this approximation may not significantly impact the outcome of the amperometry due to the particular frequency spectrum of the input signal.

In the following, particular implementations of the amperometric channel 180 and blocks 182 and 184 will be described. Further, the validity of the proposed minimization steps (i.e. removing the front-end op-amp and providing 1-bit coefficient approximation) will be set out.

Referring now to FIG. 15, shown therein is a block diagram of the amperometric channel 180 implemented by a delta-sigma front-end ADC 182. FIG. 16 illustrates a conventional implementation of a typical first order ADC used for amperometry 183 comprising a digital-to-analog converter (“DAC”) 1602, an integrator circuit 1604 comprising an op-amp 1605 and a capacitor C_(int), an op-amp 1606 and a pulse shaping block 1608. A negative feedback loop (loop 1) in the integrator 1604 creates a virtual ground at the input terminal of the ADC. Another negative feedback loop in the circuit of FIG. 16 similarly works toward making a virtual ground at input (loop 2) by keeping integrator output as close to Vref as possible. FIG. 17 illustrates an op-amp-less delta-sigma ADC 185 resulting by removing loop 1 from the conventional implementation in FIG. 16 and providing a grounded capacitor 1609. Performance of op-amp-less delta-sigma ADC in keeping a virtual ground at the input node improves by increasing the oversampling frequency and reducing the DAC coefficient.

The validity of the embodiment of the op-amp-less ADC 185 described above will now be discussed with reference to FIGS. 18 to 26.

In order for the op-amp-less potentiostat 185 shown in FIG. 17 to produce valid electrochemical measurement results, it should function approximately equivalently to the ideal circuit 183 in FIG. 16. Specifically, to conduct the electrochemical measurement shown in FIG. 13 in diagram 602, the potentiostat circuit should accurately compute the electrical impedance between the working 162 and the reference electrode 164 at a known test frequency. FIG. 18 illustrates the lumped model of an arbitrary passive medium under-test. While the lumped RC model of the medium may comprise an arbitrarily complex network 902 of resistor (“R”) and capacitor (“C”) components, at a single known frequency, the medium is accurately modeled by an equivalent parallel network 904 of one R (Ro) and one C (Co). The mathematical equivalency of the complex lumped model to the simplified parallel RoCo network at the known test frequency of wo is provided below. The goal of measurement using potentiostat is to accurately determine the values of R_(o) and C_(o) at the test frequency ω_(o).

${Z\left( \omega_{0} \right)} = {{{{Re}\left\{ {Z\left( \omega_{0} \right)} \right\}} + {j\mspace{14mu}{lm}\left\{ {Z\left( \omega_{0} \right)} \right\}}} = {\underset{\underset{R_{0}}{︸}}{{Re}\left\{ {Z\left( \omega_{0} \right)} \right\}} + {j\;\omega_{0}\mspace{14mu}\underset{\underset{C_{0}}{︸}}{{lm}\left\{ {{Z\left( \omega_{0} \right)}/\omega_{0}} \right\}}}}}$ Z(ω₀) = R₀ + j ω₀C₀

FIG. 19 illustrates the transient lumped RC model of the medium under test by the op-amp-less potentiostat 185 in FIG. 17 during the time between two consecutive sampling instances. As illustrated, during the time between two consecutive samples, the test on the medium only results in a change in the integration capacitance C_(int) of the potentiostat because all the active components of the potentiostat are off during the relevant time. Based on this model, the current entering the potentiostat, caused by applying the voltage U to the sample, creates a change in the input potential V_(f). The relationship between V_(f) and the sample under test can be determined by approximating the continuous-time output of the source U with its discrete-time equivalent values U(n−1), U(n), U(n+1), . . . as shown in FIG. 20, providing a discrete-time approximation of the source voltage signal. Similarly, the value of other signals can be denoted as the (n−1)th, nth, (n+1)th, . . . sampling instances using (n−1), (n), (n+1), . . . indices respectively. With this approximation, U remains constant and equal to U(n−1) until the next sampling instance. Upon the nth sampling instance, an ideal step signal, ΔU(n), suddenly raises the level of U to its next discrete level, U(n). By this approximation, the change in Vf between the (n−1)th and nth samples is quantified by superimposing the outcomes of the two half-circuits shown in FIG. 21, half-circuit 906 representing the constant signal U(n−1) and half-circuit 908 the ideal step signal ΔU(n) at the end of the interval. Accordingly, FIG. 21 illustrates the decomposition of the source signal into constant voltage and step signal components. The constant voltage U(n−1) creates a current through R0 while the C0 blocks the constant U(n−1) entirely. Conversely, the ideal step voltage ΔU(n) changes Vf through C0 instantly at the nth sampling moment but, at the same instant, is blocked by Ro entirely.

FIG. 22 illustrates the z-domain model of the ideal integrator in a conventional ΔΣ-ADC-based potentiostat, as shown in FIG. 16, based on the discrete-time approximation shown in FIG. 20. The values of the coefficients δ2 and δ1 in this model are determined by the values of C₀ and the sample time constant τ=R0C0, respectively. FIG. 23 shows the derivation of the same model for the integrator in the op-amp-less potentiostat 185 in FIG. 17. As shown, removing the op-amp causes two additional branches with the weights δ2 and δ1 to appear in the z-domain model of the potentiostat. FIG. 24 shows the z-domain model of the 1-bit DAC in the op-amp-less potentiostat 185 of FIG. 17. As illustrated, an unwanted branch appears between the DAC output, Vf, and its input, V(n), when there is no op-amp in the integrator.

FIGS. 25 and 26 illustrate the whole system models of the ideal and op-amp-less ΔΣ-ADC-based potentiostats of FIG. 16 and FIG. 17, 183, 185, respectively. The whole-system models are derived by adding the quantizer block to the z-domain integrator and models in FIGS. 22 and 23, and 24, respectively.

The derivation of the whole-system z-domain transfer functions of the conventional ΔΣ-ADC-based potentiostats 183 of FIG. 16 may be as follows:

$\frac{V_{n}}{Z^{- 1}} = {{\left( {\delta_{2} + \frac{\delta_{1}}{1 - Z^{- 1}}} \right)U_{n}} - {\frac{G_{D}\delta_{3}}{C_{DAC} + C_{INT}}V_{n}}}$ $\frac{V_{n}}{U_{n}} = \frac{{\delta_{2}\left( {1 - Z^{- 1}} \right)} + \delta_{1}}{1 - Z^{- 1} + {G_{D}\delta_{3}Z^{- 1}}}$ Sel.  LSB(U_(n))  s.t.G_(D)δ₃ = 1 THEN V_(n + 1) = [δ₂(1 − Z⁻¹) + δ₁]U_(n) U = U_(m)cos  ω₀t $V = {{\frac{2\pi\; U_{m}}{j\;\omega_{clk}C_{int}}\left\lbrack {{\underset{\underset{{Re}{\{\frac{1}{Z_{0}}\}}}{︸}}{\frac{1}{R_{0}}}\cos\;\omega_{0}t} + {\underset{\underset{{lm}{\{\frac{1}{Z_{0}}\}}}{︸}}{j\;\omega_{0}C_{0}}\sin\;\omega_{0}t}} \right\rbrack}U_{n}}$

The derivation of the whole-system z-domain transfer functions of the op-amp-less ΔΣ-ADC-based potentiostat 185 of FIG. 17 may be as follows:

$\frac{V_{n}}{Z^{- 1}} = {{\left\lbrack {{\delta_{2}\left( {1 - \delta_{2}} \right)} + \frac{\delta_{1} - {{\delta_{2}\left( {1 - \delta_{2}} \right)}\delta_{3}}}{1 + \delta_{1} - {\left( {1 - \delta_{3}} \right)Z^{- 1}}}} \right\rbrack U_{n}} - {\frac{\delta_{1} - {{\delta_{2}\left( {1 - \delta_{2}} \right)}\delta_{3}}}{1 + \delta_{1} - {\left( {1 - \delta_{3}} \right)Z^{- 1}}}V_{n}}}$ IF:δ₁ ⪡ 1, δ₂ ⪡ 1, δ₃ ⪡ 1 AND Sel.LSB(U_(n))  s.t.G_(D)δ₃ = 1 THEN V_(n + 1) = [δ₂(1 − Z⁻¹) + δ₁]U_(n), U = U_(m)cos  ω₀t $V = {{\frac{2\pi\; U_{m}}{j\;\omega_{clk}C_{int}}\left\lbrack {{\underset{\underset{{Re}{\{\frac{1}{Z_{0}}\}}}{︸}}{\frac{1}{R_{0}}}\cos\;\omega_{0}t} + {\underset{\underset{{lm}{\{\frac{1}{Z_{0}}\}}}{︸}}{j\;\omega_{0}C_{0}}\sin\;\omega_{0}t}} \right\rbrack}U_{n}}$

Based on the derived z-domain transfer functions of the conventional and op-amp-less potentiostat circuits above, the op-amp-less design may be approximately equivalent to the ideal design under the some conditions, such as if: (1) parallel capacitive component of the medium C₀ being tested is much smaller than the integrating capacitance C_(int), (2) the bandwidth of the combination of the medium and the integrating capacitor C_(int) (1/R₀C_(int)) is much less than the sampling frequency (f_(s) or 1/T_(s)), and (3) the admittance of the medium under test is much less than the equivalent conductance of the I-DAC at the sampling frequency.

δ₁<<1 C₀<<C_(int): SMALL ELECTRODES

δ₂<<R₀C₀<<T_(s): HIGH OSR

δ₃<<1 G_(D)<<1: SMALL CURRENTS

In the context of some embodiments of the die and associated amperometry channel configurations described above, the condition (1) may be met due to the small size of the working electrodes (40 μm) which may cause the medium capacitance to be effectively equal to the fringe capacitance between the WE and the adjacent RE in the top layer (MA) layout 552 of FIG. 11, while C_(int) is the MIM capacitor with approximately the same size as WE implemented underneath it on the E1 layer. Condition (2) may be met by designing the ADC to work at sampling ratios as high as 100 MHz while medium frequency is limited to few kHz. Condition (3) may be met because of high oversampling and can be further improved by used a higher voltage DAC using the 3.3V devices in available in the IBM 0.13 μm standard process.

Referring now to FIG. 27 to FIG. 30, shown therein are embodiments approximating the multiplication coefficients by a single bit approximation of those values at block 184 of channel embodiment 180.

FIG. 27 shows a conventional implementation of a digital multiplication operation performed on the output of a delta sigma ADC after a decimation filter, i.e. particularly a conventional implementation of the sine and cosine waveform multiplication at ADC output. The digital coefficients are stored in memory and applied in a multibit MAC operation which requires SRAM storage, routing of a parallel bus of sin/cos coefficients to each amperometry channel, and implementation of a complete 16-bit MAC operation inside each channel.

FIG. 28 illustrates the replacement of the 16-bit coefficient multiplication by a 1-bit XOR according for block 184 of embodiment 180. By approximating the sinewave (and cosine waveforms) by a squarewave of the same frequency and phase, the multi-bit multiplication of the output of the first counter may be minimized by being replaced by a multi-bit XOR operation between the squarewave and the digital word at the output of the first counter. As the output of the first counter is reset periodically (to represent a low-pass filter), the first counter is eliminated by moving the XOR operation to the front and merging the two counters (the reset and the non-reset counters). Therefore the 16-bit digital coefficient multiplication and accumulation is replaced by a 1-bit XOR and a 1-bit counting operation.

FIGS. 29 and 30 illustrate possible representations of decibels relative to full scale (“dbFS”) against frequency for down-conversion of a signal by an ideal sine wave and a squarewave approximation, respectively. As shown in FIG. 29, multiplying the output of the sigma delta ADC by a high-resolution multibit-sinewave down-converts the target component of the ADC output spectrum to DC which is the value stored in the second counter. However, as shown in FIG. 30, the squarewave multiplication may also down-convert all the noise components occurring at the higher-order harmonics of the sinewave frequency. However, due to the noise-shaping property of the delta-sigma ADC, the down-conversion of the noise spectrum components may not corrupt the final output as the noise components folded down to DC by the first few harmonics may be minimal as compared to the signal component. As the noise components start to grow for higher harmonics, the weight of the higher order harmonics start to drop by a function of the same or more strength. Therefore, the noise shaping property of the delta-sigma ADC may effectively suppress the impact of the higher order harmonics of the squarewave during the proposed 1-bit multiplication.

Referring now to FIGS. 31 to 32, shown therein are schematic diagrams of amperometric channels implemented by conventional circuit blocks in FIG. 31, and, in FIG. 32, a power- and area-minimized implementation of the amperometric channel 180 which takes advantage of the simplifying properties of the input and output signals of the channel blocks 182 and 184 described above.

Referring now to FIGS. 33, 34 and 35, shown therein are transistor-level implementations of the different blocks of a delta-sigma ADC circuit provided in view of the embodiments described above. FIG. 33 illustrates a transistor-level schematic of a low power zero-hysteresis zero-kickback latched comparator circuit to implement the delta-sigma ADC in embodiments of the amperometric channel described above. FIG. 34 illustrates dynamic logic buffers and other pulse shaping circuits for connecting the comparator output to other clock, including the I-DAC in the feedback. FIG. 35 illustrates a block diagram of the ultra-low leakage charge pump to implement the I-DAC in the feedback.

Although the foregoing has been described with reference to certain specific embodiments, various modifications thereto will be apparent to those skilled in the art without departing from the spirit and scope of the invention as outlined in the appended claims. The entire disclosures of all references recited above are incorporated herein by reference. 

1. A potentiostat circuit comprising: a. an op-amp-less integrator circuit comprising a grounded capacitor for integration of the recorded analog signal; b. a comparator coupled to an output of the integrator circuit to reduce signal distortion thereof; c. a digital-to-analog converter providing a negative feedback loop from an output of the comparator to the output of the integrator circuit; and d. a pulse shaping block providing an output signal of the potentiostat.
 2. The potentiostat circuit of claim 7, wherein the comparator is a zero-hysteresis comparator circuit.
 3. The potentiostat circuit of claim 8, wherein the comparator circuit reduces naturally occurring hysteresis in the comparator by isolating the output of the comparator from its input.
 4. The potentiostat circuit of claim 7, wherein the op-amp-less delta-sigma ADS is coupled to the recording module array without the need for an intermediary transimpedance amplifier.
 5. A integrated circuit for electrochemically measuring target analytes of a subject comprising: a. a power coil for receiving power from a receiver device by magnetic induction; b. a microelectrode array and an associated amperometric channel array for measuring the target analytes of the subject and generating sensor readings; and c. a transmitter for wirelessly transmitting sensor readings to the receiver device.
 6. The integrated circuit of claim 11, wherein the amperometric channel array comprises an op-amp-less delta-sigma-ADC-based potentiostat and a 1 bit multiplication circuit comprising an XOR gate and a counter.
 7. The integrated circuit of claim 12, wherein the op-amp-less delta-sigma-ADC-based potentiostat comprises: a. an op-amp less integrator circuit coupled to the microelectrode array, the integrator circuit comprising a grounded capacitor for integration of the recorded analog signal; b. a comparator coupled to an output of the integrator circuit to reduce signal distortion thereof; c. a digital-to-analog converter providing a negative feedback loop from an output of the comparator to the output of the integrator circuit; and d. a pulse shaping block providing an output signal of the potentiostat.
 8. A method for in situ electrochemical imaging of target analytes of a subject comprising: a. implanting an integrated circuit on, in or adjacent to a targeted region of the subject, the integrated circuit comprising: i. a power coil for receiving power from a receiver device by magnetic induction; ii. a microelectrode array and an associated amperometric channel array for measuring the target analytes of the subject and generating sensor readings; and iii. a transmitter for transmitting sensor readings to the receiver device; b. positioning the receiver device on a surface of the subject; c. receiving sensor readings at the receiver device; and d. processing the sensor readings to diagnose risk of seizure onset in the subject.
 9. The method of claim 14, wherein the targeted region is the cortex.
 10. The method of claim 15, wherein the surface is the scalp.
 11. The method of claim 14, wherein the amperometric channel array comprises an op-amp-less delta-sigma-ADC-based potentiostat and a 1 bit multiplication circuit comprising an XOR gate and a counter.
 12. The method of claim 17, wherein the op-amp-less delta-sigma-ADC-based potentiostat comprises: a. an op-amp less integrator circuit coupled to the microelectrode array, the integrator circuit comprising a grounded capacitor for integration of the recorded analog signal; b. a comparator coupled to an output of the integrator circuit to reduce signal distortion thereof; c. a digital-to-analog converter providing a negative feedback loop from an output of the comparator to the output of the integrator circuit; and d. a pulse shaping block providing an output signal of the potentiostat 